The present invention relates to the field of serial digital data communication systems. In particular, the present invention relates to latch-up avoidance and recovery in a serial digital data receiver using a quantized feedback DC restorer.
In a digital data communication system the transmitted data is generally attenuated and distorted by the medium and the AC coupling networks through which it is transmitted. This results, among other things, in a loss of the low frequency and DC components in the received data.
To combat this problem, receivers typically include a DC (direct current) restorer to restore or regenerate the low frequency and DC components of the transmitted input, and an automatic gain control (AGC) circuit which automatically changes the gain or amplification of the received input to maintain the level of the amplified signal essentially constant despite variations in input signal strength.
DC restorer circuits are generally implemented as either a clamping DC restorer or a DC restorer based on the principle of quantized feedback (QFB). Both clamping and quantized feedback restorer circuits are described in detail in U.S. Pat. No. 5,426,389, the description of said patent being incorporated herein by this reference. A QFB DC restorer circuit generally exhibits superior noise and jitter performance, however such circuits are susceptible to latching-up if the output of the restorer is in the incorrect state at the onset of data transmission. Prior art methods of overcoming the latch-up problem involve additional start-up circuitry and/or deviations in the QFB structure, and, as a result, require supplementary circuitry and exhibit inferior circuit performance.
Further, an important criteria in designing a QFB DC restorer is the delay which occurs in the feedback loop. Since any delay in the feedback loop of the QFB restorer adversely affects the construction of the signal spectrum at the input of the slicer of the restorer, delay should be kept at a minimum level. In particular, at high data rates, elegant and efficient circuit implementation techniques are critical for keeping the QFB circuit as simple as possible.
In one aspect, the present invention is a circuit for receiving an input signal and providing a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said circuit comprising: (a) an automatic gain control (AGC) circuit for providing a gain signal which processes said input signal to output a controlled signal having a constant amplitude at either said first level or said second level, said AGC circuit being operative in a first mode to provide said gain signal in response to the difference between the level of said controlled signal and the level of said quantized output signal; (b) a restorer circuit coupled to said AGC circuit for receiving said controlled signal and for providing a quantized output signal in response; (c) a carrier detect circuit coupled to said AGC circuit and having an input for receiving said quantized output signal, said carrier detect circuit providing a detection signal for indicating the presence of a transition in the level of said quantized output signal, said detection signal being coupled to said AGC circuit; such that during periods when said detection signal indicates that there are transitions in the level of said quantized output signal, said AGC circuit is operative in said first mode, and during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal, said AGC circuit is operative in a second mode wherein said gain signal is continually increased, at least to a predetermined level.
In another aspect of the present invention, said restorer circuit comprises: (a) a high-pass filter circuit for receiving said controlled signal and providing a high-pass filtered controlled signal in response; (b) a low-pass filter circuit for receiving said quantized output signal and providing a low-pass filtered quantized output signal in response, said low pass filter circuit providing a feedback path for said low-pass filtered quantized output signal; (c) a summer for adding said high-pass filtered controlled signal with said low-pass filtered quantized output signal to provide a slicer input signal; and (d) a slicer circuit for comparing said slicer input signal to a slicer reference signal and providing said quantized output signal at a slicer output terminal in response.
Thus, in further aspects of the present invention, said low pass filter circuit includes a disabling circuit responsive to said detection signal or a version thereof, so that said disabling circuit disables said feedback path, either entirely or partially, during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.